1. Technical Field
The present invention relates to a debug support device for debugging a program, and a program for directing a computer to perform a debugging process, and more specifically to a debug support device for debugging a program executed by a processor in multiprocessor form realized by a plurality of processors, and a program for directing a computer to perform a debugging method.
2. Related Art
Recently, a tool referred to as a debugger is used in developing software of a computer. The debugger has the function of directing a computer to interrupt a program, set a break point, and perform a single step to virtually operate a processor and memory of a computer. The debugger can be an online debugger implemented by software only and an ICE (in-circuit emulator) implemented by a combination with hardware. The ICE has advanced functions but expensive. The online debugger is less expensive than the ICE, but has no equivalent functions.
The debugger sets the function of suspending a program called a “break point”. When the break point is performed, the debugger is activated. When the debugger is activated, a register, memory, I/O of a processor can be referenced and changed.
Recently, a processor capable of concurrently operating a plurality of processors by combining the plurality of processors has been developed. The processor can be a multithread processor and a multiprocessor. In this specification, a processor obtained by combining a plurality of processors such as a multithread processor, a multiprocessor, etc. is generally referred to as a multiprocessor system.
For supporting a debugging operation of a multiprocessor system, there is a technique of grasping the state of the programs of all processors executed by a multiprocessor system by stopping the processors other than a processor in which a break point occurs. The conventional technique can be, for example, JP-A-5-313946 (hereinafter referred to as patent document 1).
In the patent document 1, a system clock is stopped when a processor to be debugged reaches a break point and a stop signal is issued. At this time, the operations of all components of the entire system are simultaneously stopped, and the contents of the memory and register of all processors and the contents of the registers of other hardware modules when the operations are stopped are read. In the patent document 1, the operation states of not only a specific processor but also other hardware modules can be observed when a break point occurs.
However, in the invention according to the patent document 1, since a break point instruction raises an exception condition and the clock control unit stops the system clock, other processors cannot be stopped in one process. Moreover, the processor is stopped, for example, at the separation of a machine cycle.
Therefore, in the field of supporting the debugging of a multiprocessor system, it is desired to develop a technique of more efficiently matching the stop timing between a processor in which a break point occurs and other processors.